THESIS

Design & Building Architecture Across 30 nm, 28 nm, 7 nm, 5 nm, and 2 nm Semiconductor Nodes

Page 1 — Introduction

Semiconductor technology has undergone one of the most aggressive engineering evolutions in human history. The transition from 30 nm to 2 nm nodes represents not only geometric scaling but a complete transformation in device physics, interconnect architecture, power delivery, manufacturing constraints, and design methodologies.

While early nodes such as 30 nm and 28 nm still relied on planar CMOS, the industry’s push toward 7 nm, 5 nm, and 2 nm required radical reinvention:

• FinFET transistors
• Gate‑All‑Around (GAA) nanosheets
• Backside power delivery networks
• Extreme ultraviolet (EUV) lithography
• AI‑driven physical design automation

These nodes are not simply smaller versions of their predecessors; they are new technological ecosystems with unique design rules, constraints, and architectural paradigms.

According to industry analysis, process nodes are now commercial labels, not literal physical dimensions. The “nm” number no longer corresponds to gate length or metal pitch; instead, each node is defined by its contacted poly pitch (CPP), minimum metal pitch (MMP), transistor density, and standard‑cell track height .

This thesis provides a deep, structured, engineering‑level exploration of how chips are designed and architected across these nodes, focusing on the physical design, transistor architecture, interconnect scaling, power delivery, manufacturing technologies, and system‑level implications.

Page 2 — Evolution of Process Nodes

2.1 Historical Context of Node Scaling

Node scaling historically followed a two‑year cadence, driven by Moore’s Law. Approximate introduction years include:

• 28 nm — 2010
• 7 nm — 2018
• 5 nm — 2020
• 3 nm — 2022
• 2 nm — ~2025

Each node represents a full technology generation, introducing new:

• Design rules
• Materials
• Transistor structures
• Interconnect stacks
• Power delivery methodologies
• EDA tool requirements

2.2 Why Node Names Became Non‑Physical

By the mid‑1990s, the node name stopped representing actual transistor gate length. At advanced nodes:

• No feature on a “5 nm” chip is actually 5 nm.
• Foundries’ “same‑named” nodes differ significantly.
• What matters are real geometric parameters:
  • CPP
  • MMP
  • Transistor density
  • Standard‑cell height

This shift reflects the complexity of modern semiconductor manufacturing, where marketing labels simplify what is actually a multidimensional technology space.

Page 3 — Transistor Architecture Across Nodes

3.1 Planar CMOS (30 nm → 28 nm)

At 30 nm and 28 nm, chips still used planar MOSFETs, where the gate lies flat over the channel. Characteristics:

• Simple geometry
• Mature manufacturing
• Increasing leakage at small geometries
• Limited electrostatic control

These nodes represent the final era of planar CMOS before FinFETs became mandatory.

3.2 FinFET Era (7 nm → 5 nm)

FinFETs introduced a 3D gate structure that wraps around a vertical fin, dramatically improving:

• Gate control
• Leakage reduction
• Switching efficiency

At 7 nm and 5 nm, FinFETs became the industry standard, enabling:

• Higher transistor density
• Lower power consumption
• Better performance scaling

However, FinFET design introduced new complexities:

• Multi‑patterning lithography
• Color‑aware routing
• Increased parasitic coupling
• More complex standard‑cell libraries

3.3 Gate‑All‑Around (GAA) Nanosheets (2 nm)

At 2 nm, foundries such as TSMC and Intel introduced nanosheet GAA transistors, where the gate fully surrounds the channel. This architecture provides:

• Superior electrostatic control
• Adjustable nanosheet widths
• Higher drive current
• Better leakage suppression

TSMC began volume production of its N2 node in 2025, while Intel’s 18A node introduced RibbonFET GAA and PowerVia backside power delivery .

These innovations mark the most significant transistor redesign in decades.

Page 4 — Physical Design Complexity Across Nodes

4.1 Why Advanced Nodes Are Harder

Physical design at 28 nm involved:

• Wirelength optimization
• Timing closure
• Managing a few hundred timing corners

At 3 nm and below, physical design becomes a multi‑physics optimization problem involving:

• Waveform‑dependent delay models
• Spatial IR‑drop correlation
• Nanosheet width selection
• Backside power delivery constraints
• Chiplet‑to‑chiplet latency budgets
• Reinforcement‑learning‑driven design exploration

4.2 Interconnect Dominance

At sub‑5 nm nodes, transistor intrinsic delays are minor compared to RC delays of interconnect wires. This means:

• Layout determines circuit speed
• Routing congestion becomes a primary limiter
• Crosstalk noise increases
• Electromigration risk rises
• IR drop becomes critical

Designers must adopt physics‑aware, process‑compliant, and EDA‑integrated methodologies to manage these challenges